Binary-Coded Ternary: Difference between revisions
From T729 Balanced Ternary Computer
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This implementation is useful with logic simulators and would most likely function on an FPGA or ASIC. However because each trit needs two wires a design would be extremely bloated with interconnects and bus lines. Doubling the wiring and logic and loosing most of the advantages of a ternary computer. | This implementation is useful with logic simulators and would most likely function on an FPGA or ASIC. However because each trit needs two wires a design would be extremely bloated with interconnects and bus lines. Doubling the wiring and logic and loosing most of the advantages of a ternary computer. | ||
For a discrete component build or fully custom chip I would explore other options that do not waste so chip much space | For a discrete component build or fully custom chip I would explore other options that do not waste so chip much space. | ||
<div style="text-align: center;"> | <div style="text-align: center;"> | ||
Revision as of 16:38, 21 June 2024
Dual Binary is an implementation of ternary logic built on top of normal binary logic. Using two bits or wires per trit as the base. Sub-circuits made with binary logic gates can emulate the truth tables of ternary logic gates.
This implementation is useful with logic simulators and would most likely function on an FPGA or ASIC. However because each trit needs two wires a design would be extremely bloated with interconnects and bus lines. Doubling the wiring and logic and loosing most of the advantages of a ternary computer.
For a discrete component build or fully custom chip I would explore other options that do not waste so chip much space.
| Dual Binary | ||
| N | P | T |
| 0 | 0 | 0 |
| 0 | 1 | + |
| 1 | 0 | - |
| 1 | 1 | ? |
