Binary-Coded Ternary

Dual Binary is an implementation of ternary logic built on top of normal binary logic. Using two bits or wires per trit as the base. Sub-circuits made with binary logic gates can emulate the truth tables of ternary logic gates.

This implementation is useful with logic simulators and would most likely function on an FPGA. However because each trit needs two wires a design would be extremely bloated with interconnects and bus lines. Doubling the wiring and logic and loosing most of the advantages of a ternary computer.

For a discrete component build or fully custom chip I would explore other options that do not waste so much chip space.

Dual Binary
N	P	T
0	0	0
0	1	+
1	0	-
1	1	?