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<div class="hcat"> | <div class="hcat"> | ||
== Wiki == | == Wiki == | ||
* [[T729:About|About]] | * [[T729:About|About]] | ||
* [[Project Goals]] | * [[Project Goals]] | ||
</div | </div> | ||
== Logic Gates == | <div class="hcat"> | ||
<div class="hcat"> | == Logic Gates == | ||
=== Ternary === | <div class="hcat"> | ||
* 2 Input | === Ternary === | ||
** [[SUM (Ternary Gate)|SUM]] | * 2 Input | ||
** [[CON (Ternary Gate)|CON]] | ** [[SUM (Ternary Gate)|SUM]] | ||
** [[ANY (Ternary Gate)|ANY]] | ** [[CON (Ternary Gate)|CON]] | ||
** [[XOR (Ternary Gate)|XOR]] | ** [[ANY (Ternary Gate)|ANY]] | ||
** [[COM (Ternary Gate)|COM]] | ** [[XOR (Ternary Gate)|XOR]] | ||
** [[MAX (Ternary Gate)|MAX]] | ** [[COM (Ternary Gate)|COM]] | ||
** [[MIN (Ternary Gate)|MIN]] | ** [[MAX (Ternary Gate)|MAX]] | ||
* 1 Input | ** [[MIN (Ternary Gate)|MIN]] | ||
** [[NEG (Ternary Gate)|NEG]] | * 1 Input | ||
** [[INC (Ternary Gate)|INC]] | ** [[NEG (Ternary Gate)|NEG]] | ||
** [[DEC (Ternary Gate)|DEC]] | ** [[INC (Ternary Gate)|INC]] | ||
</div> | ** [[DEC (Ternary Gate)|DEC]] | ||
<div class="hcat"> | </div> | ||
=== Binary === | <div class="hcat"> | ||
* 2 Input | === Binary === | ||
** [[AND (Binary Gate)|AND]] | * 2 Input | ||
** [[OR (Binary Gate)|OR]] | ** [[AND (Binary Gate)|AND]] | ||
** [[XOR (Binary Gate)|XOR]] | ** [[OR (Binary Gate)|OR]] | ||
* 1 Input | ** [[XOR (Binary Gate)|XOR]] | ||
** [[NOT (Binary Gate)|NOT]] | * 1 Input | ||
</div> | ** [[NOT (Binary Gate)|NOT]] | ||
</div> | </div> | ||
</div> | |||
<div class="hcat"> | <div class="hcat"> | ||
== Computer == | |||
* [[Terminal]] | |||
* [[Data Storage]] | |||
</div> | |||
== Processor == | <div class="hcat"> | ||
* [[Ternary Operations]] | == Processor == | ||
* [[ALU]] | * [[Ternary Operations]] | ||
* [[Registers]] | * [[ALU]] | ||
* [[Instruction Set Map]] | * [[Registers]] | ||
* [[Memory]] | * [[Instruction Set Map]] | ||
* [[IO]] | * [[Memory]] | ||
</div> | * [[IO]] | ||
</div> | |||
== | <div class="hcat"> | ||
* [[ | == Programming == | ||
* [[ | * [[Heptavintimal]] | ||
</div> | * [[Construct]] | ||
* [[T Language]] | |||
</div> | |||
<div class="hcat"> | <div class="hcat"> | ||
== | == Logic Simulation == | ||
* [ | * [https://circuitverse.org/simulator/t729-balanced-ternary-cpu CircuitVerse.org] | ||
</div> | |||
</div> | |||
<div class="hcat"> | <div class="hcat"> | ||
== | == Implementation == | ||
* [ | * [[Dual Binary]] | ||
</div> | * [[Low Open High]] | ||
* [[Discrete Component]] | |||
* [[FPGA]] | |||
* [[ASIC]] | |||
* [[Full Custom Chip]] | |||
</div> | |||
<div class="hcat"> | <div class="hcat"> | ||
== Discord == | |||
<div style="text-align: center;"> | |||
This wiki is for documentation.<br /> | |||
Current discussions and work is on Discord.<br /> | |||
<b>https://discord.gg/3an392s3vZ</b> | |||
</div> | |||
</div> | |||
== Discord == | |||
<div style="text-align: center;"> | |||
This wiki is for documentation.<br /> | |||
Current discussions and work is on Discord.<br /> | |||
<b>https://discord.gg/3an392s3vZ</b> | |||
</div> | |||
</div> | |||
</div> | </div> | ||
Revision as of 17:28, 18 June 2024
Hobby balanced ternary computer project. Work in progress.
== Wiki == * About * Project Goals
== Logic Gates ==
== Computer == * Terminal * Data Storage
== Processor == * Ternary Operations * ALU * Registers * Instruction Set Map * Memory * IO
== Programming == * Heptavintimal * Construct * T Language
== Logic Simulation == * CircuitVerse.org
== Implementation == * Dual Binary * Low Open High * Discrete Component * FPGA * ASIC * Full Custom Chip
== Discord ==
This wiki is for documentation.
Current discussions and work is on Discord.
https://discord.gg/3an392s3vZ
