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From T729 Balanced Ternary Computer
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12 March 2025
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18:01 | Data Storage 3 changes history +85 [MrDyne (3×)] | |||
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18:01 (cur | prev) +58 MrDyne talk contribs | ||||
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18:00 (cur | prev) −1 MrDyne talk contribs | ||||
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17:59 (cur | prev) +28 MrDyne talk contribs |
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17:43 | Ternary vs Binary 4 changes history +699 [MrDyne (4×)] | |||
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17:43 (cur | prev) −43 MrDyne talk contribs | ||||
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17:42 (cur | prev) +67 MrDyne talk contribs | ||||
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17:40 (cur | prev) +160 MrDyne talk contribs | ||||
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17:39 (cur | prev) +515 MrDyne talk contribs |
11 March 2025
00:26 | T729:About diffhist +81 MrDyne talk contribs |
N 00:03 | Discrete Component diffhist +744 MrDyne talk contribs (Created page with "Building a discrete component ternary computer implemented in BCT would actually be quite doable with fast switching SMT MOSFETs and cheap custom PCBs. NPN/PNP CMOS logic gate layouts would result in low power usage. It would not be a cheap project but there is no reason it would not function if obviously build correctly. Another option is using standalone fast switching discrete SMT logic gates. If I ever get around to learning how to create...") |
10 March 2025
23:29 | NZP diffhist +87 MrDyne talk contribs |
23:27 | Low Open High diffhist −34 MrDyne talk contribs |
17:57 | Deletion log MrDyne talk contribs deleted page Unsorted Pages (content was: "* Add", and the only contributor was "MrDyne" (talk)) |
17:56 | CON (Ternary Gate) diffhist +62 MrDyne talk contribs |
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17:45 | Add (Ternary) 2 changes history +88 [MrDyne (2×)] | |||
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17:45 (cur | prev) +13 MrDyne talk contribs | ||||
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17:44 (cur | prev) +75 MrDyne talk contribs |
N 17:41 | FPGA diffhist +846 MrDyne talk contribs (Created page with "I do not have any hands-on experience with FPGAs yet and do not want to get into FPGAs until I have a stable T729 design already. I won't know what size FPGA to get until the T729 architecture is mostly complete. Large FPGAs can get quite expensive. I foresee some limitations running a ternary project on an FPGA. * FPGAs can only do binary. Must use ADC and DACs to handle analog signals. ** Only BCT implementation would work on an FPGA. * Memory...") |